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W948D6FB / W948D2FB
256Mb Mobile LPDDR
7.6.1 Write Command
CK
CK
CKE
CS
RAS
CAS
WE
A0-An
A10
BA0,BA1
(High)
CA
Enable AP
AP
Disable AP
BA
= Don't Care
BA=BANK Address
CA=Coulmn Address
AP=Auto Precharge
7.6.2 Basic Write Timing Parameters
Basic Write timing parameters for DQs are shown in figure below; they apply to all Write operations.
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing
coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the memory;
if the DM signal is registered High, the corresponding data inputs will be ignored, and a write will not be executed to
that byte / column location.
CK
t CK
t CH
t CL
Case 1:
CK
t DQSS
t DQSH
t DSH
t DSH
tDQSS =
min
DQS
t WPRES
t WPRE
t DS
t DH
t DQSL
t WPST
Case 2:
tDQSS =
max
DQ, DM
DQS
t WPRES
DI
n
t DQSS
t DS
t DQSH
t WPRE
t DH
t DSS
t DQSL
t DSS
t WPST
DQ, DM
1) DI n=Data In for column n
DI
n
= Don't Care
2) 3 subsequent elements of Data In are applied in the programmed order following DI n.
3) tDQSS: each rising edge of DQS must fall within the +/-25% window of the corresponding positive
clock edge.
Publication Release Date : Oct, 15, 2012
- 34 -
Revision : A01-004
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